1. Field of the Invention
The present invention relates to charge coupled devices (CCD) typically used to capture color pictures in digital form, and more specifically to a method and apparatus for correcting the offset which is applied to the output of the CCDs.
2. Related Art
Charge coupled devices (CCDs) are often used to capture images received in the form of light. A CCD typically contains several pixels, with each pixel holding an amount of charge proportionate to the intensity of incident light and the length of time the light is allowed to fall on the pixel. The charge can be later translated to a voltage level and/or digital data for further processing and/or storing (in mass non-volatile storage). CCDs thus find application in devices such as digital cameras and scanners as is well known in the relevant arts.
A correction (termed xe2x80x9coffset correctionxe2x80x9d) is often applied to the output (i.e., voltage or digital data in the above paragraph) of a CCD typically to compensate for (or eliminate) undesirable components which may be present in the CCD output. For example, the charge generated by a CCD should ideally be entirely generated by the incident light but other phenomenon such as thermally generated electron-hole pairs add to the charge.
Such additions are undesirable, for example, because a later reproduced image may be brighter than that represented by the light incident on the CCD. Accordingly, it is desirable that the undesirable components be eliminated, and the corresponding correction is termed as offset correction. The extent to which a correction is applied, is referred to as an offset, and the act of applying the offset to the CCD output may be referred to as offset correction.
To facilitate the removal of such undesirable components, CCDs often include black pixels which are shielded from light when the active pixels are exposed to light. The charge in the black pixels may be deemed to represent the undesirable components to some extent, and accordingly the offset to the CCD charge is computed based on the charge present in the black pixels. The offset is thus subtracted from the CCD outputs to generate the true image (close to the image represented by the incident light).
One problem with the above noted approach of offset correction is that some of the black pixels may be xe2x80x9cstuckxe2x80x9d at a high charge level, for example, due to manufacturing defects. Such pixels are commonly referred to as hot pixels. An assumption that the charge related to hot pixels represents undesirable components, may lead to over correction of the output values of the CCDs. The resulting display artifacts are generally undesirable. Accordingly, it may be desirable to detect the presence of hot pixels and take any appropriate corrective action.
In one prior solution, a digital value representing the charge level of each black pixel is compared to a threshold value, and the black pixel is deemed to be a hot pixel if the corresponding digital value exceeds the threshold value. Hot pixels may be ignored from the computation of the offset correction.
One problem with such a prior solution is that the offset voltages may initially (e.g., at boot-up or when a new image is to be processed) be set to a small value with the result that a smaller value than that corresponding to the actual undesired components, may be subtracted from each of the output values. The result of the subtraction may be amplified prior to examination which determines whether corresponding pixels are hot pixels. As the error component is also amplified and contained within the examined values, the pixels may erroneously be determined to be hot pixels.
In the prior solution, all hot pixels may be ignored with respect to offset correction and thus the error component may manifest as artifacts in any reproduced images. Accordingly, the prior solution may be unacceptable at least in some environments. Therefore, what is needed is a method and apparatus which enables the hot pixels to be accurately detected so that any necessary corrective action can be undertaken.
Another typical requirement in the reproduction of images is that the offset be quickly computed such that the image can be reproduced quickly without display artifacts. Usually, the offset is computed iteratively and it is desirable that the offset converge to the correct value (representing the undesirable components) in a few iterations. In addition to fast convergence, it is desirable that adequate control be provided to correct the image by offsets of small granularity.
While quick convergence to the accurate offset value is desirable, it may be further desirable not to change substantially the offset within an image frame as such changes may result in display artifacts in the form of bands in the reproduced image. Therefore, what is needed is a flexible method and apparatus to correct the outputs of a CCD such that the corrected outputs accurately represent the image represented by the light incident on the CCD.
The present invention enables a digital representation of an image to be generated accurately. A charge coupled device (CCD) is first exposed to light from the image. The CCD typically contains active pixels which are charged proportionate to the intensity of the incident light and the time of incidence of the light. However, the charge may contain undesirable components (such as what is referred to as thermal noise). The present invention enables the undesirable components to be eliminated by examining the charge on the black pixels, which are not exposed to light.
According to an aspect of the present invention, the charge on each pixel is converted to voltage. A black pixel is determined to be a hot pixel if the voltage level of the black pixel exceeds the voltage level of a previous pixel by a specified amount. As the probability of two consecutive pixels being hot is low, the hot pixels may be detected accurately with a substantially high probability. The hot pixels may be ignored from the computation of an offset used to correct the voltage levels of the active pixels.
According to another aspect of the present invention, the offset may be computed by generating a weighted average of the voltages of black pixels in several lines. When a present black pixel is determined to be a hot pixel, the previous pixel (or voltage thereof) is substituted for the present black pixel. As the number of pixels used in computing average is always the same, the implementation of division operation may be simplified.
According to yet another aspect of the present invention, when a first pixel of a line is determined to be a hot pixel, the second pixel is provided in lieu of the first pixel in the computation of the average. In one embodiment, an adder adds the each present pixel digital value to a previous sum to generate a previous sum for the next iteration. To ensure that the average is generated without much pipeline delay, the difference of the first and second pixels is computed. When the first pixel is determined to be a hot pixel, the difference is subtracted from the previous sum (containing only the digital value of the first pixel), and the result is provided as the previous sum. As a result, the adder generates two times the value of the second pixel (i.e., second pixel is provided in lieu of first pixel), and the average is generated without much pipeline delay.
According to one more aspect of the present invention, the offset is incremented proportionate to the additional correction sought to be attained. As a result, convergence to the accurate offset (corresponding to the desired correction) may be quickly attained. In an embodiment, any change in the offset is clipped off at a ceiling (offset difference ceiling) to prevent bands in a reproduced image. That is, an upper limit is set to the change in brightness in adjacent areas due to the correction.
Yet another aspect of the present invention provides a designer the ability to control the correction range and to attain low correction resolution while minimizing the introduction of further undesirable components in the CCD output voltages as described below in the below paragraphs. The correction range refers to the maximum voltage correction (assuming zero voltage to be the minimum) that may be attained by the operation of various components of the offset correction circuit. Resolution refers to the minimum amount of correction of the output voltage that can be attained by the offset correction circuit.
In order to minimize the noise (i.e. addition of undesirable components noted above) and electrical power consumed, the number of stages in the signal path (or forward channel or path the signal takes from input till it gets converted to digital data) should generally be minimum. According to an aspect of the present invention, only two stages are required to achieve the required gain. Correlated double sampling operation is performed in the first stage, while attaining some amount of gain. The second stage is used to attain the remainder of the desired gain using a programmable gain amplifier (PGA). While the described embodiments contain only two stages, it should be understood that several aspects of the present invention can be implemented using a different number of stages.
In addition, while a solution could be implemented using only a single DAC (to achieve correction to the input signal), the same would typically require a DAC of very high resolution, which provides challenges in implementation and would normally consume more power. Thus, according to another aspect of the present invention, two DACs are used, once called the coarse DAC (CDAC) which is connected to a correlation double sampler (CDS) located in the first stage, and the second DAC, called the fine DAC (FDAC), is connected to the PGA in the second stage.
CDS may be implemented to amplify the input signal (voltage from the CCD) while partially correcting the signal. The correction may be controlled by a first capacitor (Ccdac) driven by the CDAC. The input signal may be received via a second capacitor (Csinp). The second input of both the first capacitor and the second capacitor are coupled to a feedback capacitor (Cfcds) implemented in conjunction with the CCD.
As would be readily appreciated, the gain of the input signal component (as present at the output of the CCD) is determined by the ratio Csinp/Cfcds. Assuming that the voltage applied at the output of CDAC equal Vcdac and that the input voltage equals Vi, the total output (Vcds) of the CCD equals ((Vi*Csinp/Cfcds)xe2x88x92(Vcdac*Ccdac/Cfcds)), wherein xe2x80x98*xe2x80x99 represents a multiplication operation. The capacitors and their capacitance values are represented by the same reference labels in the present application.
According to an aspect of the present invention, the ratio of Ccdac to Csinp is maintained to be a constant, which allows the offset effected to be independent of the voltage level Vi. The need for such independence may be appreciated by first understanding that it may be desirable to amplify the input signals to a degree which is inversely proportionate to the maximum possible amplitude (or range, if minimum is not equal to zero) of the input signal. Typically, the ratio of Ccdac/Cfcds is controlled to attain the desired amplification of the input signal in the first stage. By maintaining Ccdac/Csinp to be a constant, the offset correction due to the first stage can be determined by Vcdac, which in turn is determined by a numerical input to CDAC.
The output of the CDS may be connected to a capacitor Cspga, which in turn is corrected to the PGA of the second stage. Offset correction is further effected by a capacitor (Cfdac) driven by a fine DAC (FDAC). The second input of both Cspga and Cfdac is connected to a feedback capacitor (Cfpga) associated with the PGA. The output of PGA (Vpga) may be given by the equation ((Vcds*Cspga/Cfpga)xe2x88x92(Vfdac*Cfdac/Cfpga)), wherein Vfdac represents the output voltage of the FDAC.
According to another aspect of the present invention, the ratio of Cfdac to Cfpga is maintained to be a constant, which allows the correction resolution to potentially equal a least significant bit of an ADC (used to sample the output of the PGA). That is, the present invention allows offset correction to be effected by minute (small) amounts limited only by the resolution of a later sampling ADC.
Thus, once total desired amplification of the input signal (Vi) is determined, partial amplifications for each of the two stages may be assigned. The capacitances (Csinp, Cspga, Cfpga and Cfcds) may be configured consistent with the assigned partial amplifications. The capacitances Ccdac and Cfdac may be configured consistent with the objectives noted above with reference to correction range and correction resolution. By using the features of the present invention, offset correction, which quickly removes (at least substantially) the undesirable components, may be implemented.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.